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Espressif Systems /ESP32-H2 /PARL_IO /TX_GENRL_CFG

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Interpret as TX_GENRL_CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TX_IDLE_VALUE0 (TX_GATING_EN)TX_GATING_EN 0 (TX_VALID_OUTPUT_EN)TX_VALID_OUTPUT_EN

Description

Parallel TX general configuration register.

Fields

TX_IDLE_VALUE

Configures bus value of transmitter in IDLE state.
TX_GATING_EN

Set this bit to enable the clock gating of output tx clock.
TX_VALID_OUTPUT_EN

Set this bit to enable the output of tx data valid signal.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data